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max153 1msps, p-compatible, 8-bit adc with 1a power-down general description the max153 high-speed, microprocessor (p)-compatible, 8-bit analog-to-digital converter (adc) uses a half-flash technique to achieve a 660ns conversion time, and digitiz - es at a rate of 1m samples per second (msps). it operates with single +5v or dual 5v supplies and accepts either unipolar or bipolar inputs. a powerdn (power-down) pin reduces current consumption to a typical value of 1a (with 5v supply). the part returns from power-down to normal operating mode in less than 200ns, providing large reductions in supply current in applications with burst- mode input signals. the max153 is dc and dynamically tested. its p interface appears as a memory location or input/output port that requires no external interface logic. the data outputs use latched, three-state buffered circuitry for direct connection to a p data bus or system input port. the adcs input/ reference arrangement enables ratiometric operation. applications cellular telephones portable radios battery-powered systems burst-mode data acquisition digital-signal processing telecommunications high-speed servo loops features 660ns conversion time power-up/power-down in 200ns internal track/hold 1msps throughput low power 40mw (operating mode) 5w (power-down mode) 1mhz full-power bandwidth 20-pin narrow dip, so, and ssop packages no external clock required unipolar/bipolar inputs single +5v or dual 5v supplies ratiometric reference inputs 19-4740; rev 2; 1/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max153.related . functional diagram 4-bit flash adc 4-bit flash adc (4 lsb) timing and control circuitry max153 gnd mode wr/rdy cs rd int v ss three- st at e drivers d0?d7d ata outpins 2?5, 14?17 18 1211 v ref+ v ref- 1 v in pwrdn 4-bit dac v ref+ 16 7 6 3 7 7 19 v dd 20 10 downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 2 electrical characteristics (v dd = +5v 5%, v gnd = 0v; unipolar input range: v ss = gnd, v ref+ = 5v, v ref- = gnd; bipolar input range: v ss = -5v 5%, v ref+ = 2.5v, v ref- = -2.5v; 100% production tested, specifications are given for rd mode (mode = gnd), t a = t min to t max , unless otherwise noted.) (all voltages referenced to gnd.) v dd .......................................................................... -0.3v to +7v v ss .......................................................................... +0.3v to -7v digital input voltage ............................... +0.3v to (v dd + 0.3v) digital output voltage .............................. -0.3v to (v dd + 0.3v) v ref+ , v ref+ , v in ........................ (v ss - 0.3v) to (v dd + 0.3v) continuous power dissipation (t a = +70c) pdip (derate 11.11mw/c above + 70c). ................. 889mw so(w) (derate 10.00mw/c above +70c ..................800mw ssop (derate 8.00mw/c above +70c) ................... 640mw operating temperature ranges max153c ................................................................... 0 to +70c max153e ........................................................... -40c to +85c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter symbol conditions min typ max units accuracy resolution n 8 bits total unadjusted error tue unipolar range 1 lsb differential nonlinearity dnl no missing codes guaranteed 1 lsb zero-code error bipolar input range 1 lsb full-scale error bipolar input range 1 lsb dynamic specifications (note 1)signal-to-noise plus distortion noise sinad f sample = 1mhz, f in = 195.8khz 45 db total harmonic distortion thd f sample = 1mhz, f in = 195.8khz -50 db peak harmonic or spurious noise f sample = 1mhz, f in = 195.8khz -50 db conversion time (wr-rd mode) (note 2) t cwr t a = +25c, t rd < t intl , c l = 20pf 660 ns conversion time (rd mode) t crd t a = +25c 700 ns t a = t min to t max 875 full-power bandwidth v in = 5v p-p 1 mhz input slew rate 3.14 15 v/s analog input input voltage range v in v ref- v ref+ v input leakage current i in -5v v in +5v 3 a input capacitance c in 22 pf reference input reference resistance r ref 1 2 4 k? v ref+ input voltage range v ref- v dd v v ref- input voltage range v ss v ref+ v downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) (v dd = +5v 5%, v gnd = 0v; unipolar input range: v ss = gnd, v ref+ = 5v, v ref- = gnd; bipolar input range: v ss = -5v 5%, v ref+ = 2.5v, v ref- = -2.5v; 100% production tested, specifications are given for rd mode (mode = gnd), t a = t min to t max , unless otherwise noted.)note 1: bipolar input range, v in = 2.5v p-p . wr-rd mode. note 2: see figure 1 for load circuit. parameter defined as the time required for the output to cross +0.8v or +2.4v. note 3: guaranteed by design. note 4: tested with cs , rd , pwrdn at cmos logic levels. power-down current increases to several hundred) a at ttl levels. parameter symbol conditions min typ max units logic inputs input high voltage v inh cs , wr , rd , pwrdn 2.4 v mode 3.5 input low voltage v inl cs , wr , rd , pwrdn 0.8 v mode 1.5 input high current i inh cs , rd , pwrdn 1 a wr 3 mode 50 200 input low current i inl cs , wr , rd , pwrdn 1 a input capacitance (note 3) c in cs , wr, rd , pwrdn , mode 5 8 pf logic outputs output low voltage v ol i sink = 1.6ma, int , d0Cd7 0.4 v rdy, i sink = 2.6ma 0.4 output high voltage v oh i source = 360a, int , d0Cd7 4 v floating state current i lkg d0Cd7, rdy 3 a floating capacitance (note 3) c out d7Cd0, rdy 5 8 pf power requirements positive supply voltage v dd 5% for speciied accuracy 5 v negative supply voltage (unipolar operation) v ss gnd v negative supply voltage (bipolar operation) v ss 5% for speciied accuracy -5 v v dd supply current i dd v cs = v rd = 0v, v pwrdn = 5v max153c 8 15 ma max153e 8 20 power-down vdd current v cs = v rd = 5v, v pwrdn = 0v (note 4) 1 100 a v ss supply current i ss v cs = v rd = 0v, v pwrdn = 5v 25 100 a power-down v ss current v cs = v rd = 5v, v pwrdn = 0v 12 100 a power-supply rejection psr v dd = 4.75v to 5.25v, v ref + = 4.75v (max), unipolar mode 1/16 1/4 lsb downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 4 timing characteristics (note 5) (v dd = +5v 5%, v ss = 0v for unipolar input range, v ss = -5v 5% for bipolar input range, 100% production tested, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units cs to rd / wr setup time t css 0 ns cs to rd / wr hold time t csh 0 ns cs to rdy delay (note 6) t rdy c l = 50pf 70 ns t a = t min to t max , c l = 50pf 85 data-access time (rd mode) (note 2) t acc0 c l = 20pf t crd + 25 ns t a = t min to t max , c l = 20pf t crd + 30 c l = 100pf t crd + 50 t a = t min to t max , c l = 100pf t crd + 65 rd to int delay (rd mode) t inth c l = 50pf 50 80 ns t a = t min to t max , c l = 50pf 85 data-hold time (note 7) t dh 60 ns t a = t min to t max 70 delay time between conversions (acquisition time) t p 160 ns t a = t min to t max 185 write pulse width t wr 0.250 10 s t a = t min to t max 0.280 10 delay time between wr and rd pulses t rd 250 ns t a = t min to t max 350 rd pulse width ( wr - rd mode) determined by t acc1 t read1 figure 6 160 ns t a = t min to t max , figure 6 205 data-access time ( wr - rd mode (note 2) t rd < t inl t acc1 c l = 20pf, figure 6 160 ns t a = t min to t max , c l = 20pf, figure 6 205 c l = 100pf, figure 6 185 t a = t min to t max , c l = 100pf, figure 6 235 rd to int delay t ri 150 ns t a = t min to t max 185 wr to int delay t intl c l = 50pf 380 500 ns t a = t min to t max , c l = 50pf 610 rd pulse width (wr-rd mode) determinted by t acc2 t rd > t intl t read2 figure 5 65 ns t a = t min to t max , figure 5 75 data-access time (wr-rd mode) (note 2) t rd > t intl t acc2 c l = 20pf, figure 5 65 ns t a = t min to t max , c l = 20pf, figure 5 75 c l = 100pf, figure 5 90 t a = t min to t max , c l = 100pf, figure 5 110 downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 5 timing characteristics (note 5) (continued) (v dd = +5v 5%, v ss = 0v for unipolar input range, v ss = -5v 5% for bipolar input range, 100% production tested, t a = +25c, unless otherwise noted.)note 5: input control signals are specified with t r = t t = 5ns, 10% to 90% of +5v and timed from a 1.6v voltage level. note 6: r l = 5.1k pullup resistor. note 7: see figure 2 for load circuit. parameter defined as the time required for data lines to change 0.5v . figure 1. load circuits for data-access time test figure 2. load circuits for data-hold time test parameter symbol conditions min typ max units wr to int delay (pipelined mode) t ihwr c l = 50pf 80 ns t a = t min to t max , c l = 50pf 100 data-access time after int (note 2) t id c l = 20pf 30 ns t a = t min to t max , c l = 20pf 35 c l = 100pf 45 t a = t min to t max , c l = 100pf 60 c l 3k dgnd dn a . high-z to v oh b. high-z to v ol c l 3k dgnd dn +5v 10pf 3k dgnd dn a . v oh t o high-z b. v ol to high-z 10pf 3k dgnd dn +5v downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down maxim integrated 6 www.maximintegrated.com typical operating characteristics conversion time vs. ambient temperature max153 toc01 temperature (c) t crd (normalized to value at +25c) 120 100 60 80 -20 0 20 40 -40 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.50.6 -60 140 v dd = +5.25v v dd = +4.75v v dd = +5v signal-to-noise ratio max153 toc03 -100 0 500 400 300 200 100 -80 0 -20-40 -60 frequency (khz) t a = +25c input frequency = 195.8ksps (2.5v) sample frequency = 1mhz snr = 49.1db ratio (db) effective bits vs. input frequency, wr-rd mode max153 toc02 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 frequency (khz) 1k 100 10 effective bits room cold -55c i sample = 1mhz v in = 2.5v hot +125c intermodulation distortion max153 toc04 -100 0 250 200 150 100 50 -80 0 -20-40 -60 frequency (khz) t a = +25c input frequency= 94.97khz = 84.72khz (2.5v) sample frequency = 500khz imd: 2nd-order terms = -66.2db 3rd-oreder terms = -60.0db ratio (db) downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 7 pin description pin coniguration * see the digital interface section. pin name function 1 v in analog input. range is v ref - > v in < v ref+ . 2 d0 three-state data output (lsb) 3C5 d1Cd3 three-state data outputs 6 wr /rdy write control input/ready status output* 7 mode mode selection input. internally pulled low with a 50a current source. mode = 0 activates read mode. mode = 1 actives write-read mode* 8 rd read input. must be low to access data*. 9 int interrupt output goes low to indicate end of conversion*. 10 gnd ground 11 v ref- lower limit of reference span. sets the zero-code voltage. range is v ss < v ref- < v ref+ . 12 v ref+ upper limit to reference span. sets the full-scale input voltage. range is v ref- < v ref+ < v dd . 13 cs chip select input. must be low for the device to recognize wr or rd inputs. 14C16 d4Cd6 three-state data outputs 17 d7 three-state data output (msb) 18 pwrdn powerdown input. reduces supply current when low. cs must be high during power-down. 19 v ss negative supply. unipolar: v ss = 0v, bipolar: v ss = -5v. 20 v dd positive supply, +5v 2019 18 17 16 15 13 12 3 4 5 6 8 v dd v ss pwrdnd7 (msb) d2 d1 d0 (lsb) v in top view max153 d6 d5 cs rd wr/rdy 14 7 d4 mode 11 10 v ref- gnd 12 9 v ref+ int d3 pdip/so(w)/ssop + downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 8 detailed description converter operation the max153 uses a half-flash conversion technique (see the functional diagram ) in which two 4-bit flash adc sections achieve an 8-bit result. using 15 comparators, the flash adc compares the unknown input voltage to the reference ladder and provides the upper 4 data bits. an internal digital-to-analog converter (dac) uses the 4 most significant bits (msbs) to generate the analog result from the first flash conversion and a residue voltage that is the difference between the unknown input and the dac voltage. the residue is then compared again with the flash comparators to obtain the lower 4 data bits (lsbs). power-down mode in burst-mode or low sample-rate applications, the max153 can be shut down between conversions, reduc - ing supply current to microamp levels. a ttl/cmos log - ic-low on the pwrdn pin shuts the device down, reduc - ing supply current to typically 1a when powered from a single 5v supply. cs must be high when power- down is used. a logic-high on pwrdn wakes up the max153. a new conversion can be started ( wr asserted low) within 360ns of the pwrdn pin being driven high 200ns to power up plus 160ns for track/hold acquisition). if power- down mode is not required, connect pwrdn to v dd . once the max153 is in power-down mode, lowest sup - ply current is drawn with mode low (rd mode) due to an internal 50a pulldown resistor at this pin. cs must remain high during shutdown because the max153 may attempt to start a conversion that it cannot complete. in addition, for minimum current consumption, other digital inputs should remain stable in power-down. rdy, an open-drain output (in rd mode), will then fall and remain low throughout. power-down, sinking additional supply current unless cs remains high. see the reference sec - tion for information on reducing reference current during power-down. digital interface the max153 has two basic interface modes set by the status of the mode input pin. when mode is low, the converter is in the rd mode; when mode is high, the converter is set up for the wr-rd mode. read mode (mode = 0) in rd mode, conversion control and data access are con - trolled by the rd input (figure 3). the comparator inputs track the analog input voltage for the duration of t p . a minimum of 160ns is required for the input to be acquired. a conversion is initiated by driving rd low. with ps that can be forced into a wait state, hold rd low until output data appears. the p starts the conversion, waits, and then reads data with a single read instruction. wr /rdy is configured as a status output (rdy) in rd mode, where it can drive the ready or wait input of a p. rdy is an open-collector output (with no internal pullup) that goes low after the falling edge of cs and goes high at the end of the conversion. if not used, the wr /rdy pin can be left unconnected. the int output goes low at the end of the conversion and returns high on the rising edge of cs or rd . write-read mode (mode = 1) figures 4 and 5 show the operating sequence for the write-read (wr-rd) mode. the comparator inputs track the analog input voltage for the duration of t p . a minimum of 160ns is required for the input voltage to be acquired. the conversion is initiated by a falling edge of wr . when wr returns high, the 4 msbs flash result is latched into the output buffers and the 4 lsbs conversion begins. int goes low about 380ns later, indicating conversion end, and the lower 4 data bits are latched into the output buf - fers. the data is then accessible 65ns to 130ns after rd goes low (see the timing characteristics ). if an externally controlled conversion time is required, drive rd low 250ns after wr goes high. this latches the lower 4 data bits and outputs the conversion result on d0C07. a minimum 160ns delay is required from int going low to the start of another conversion ( wr going low). options for reading data from the converter include the following: using internal delay the p waits for the int output to go low before reading the data (figure 4). int typically goes low 380ns after the rising edge of wr , indicating the conversion is complete, and the result is available in the output latch. with cs low, data outputs d0Cd7 can be accessed by pulling rd low. int is then reset by the rising edge of cs or rd . downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 9 fastest conversion: reading before delay an external method of controlling the conversion time is shown in figure 5. the internally generated delay t intl varies slightly with temperature and supply voltage, and can be overridden with rd to achieve the fastest conversion time. int is ignored, and rd is brought low typically 250ns after the rising edge of wr . this completes the conversion and enables the output buffers (d0Cd7) that contain the conversion result. int also goes low after the falling edge of rd and is reset on the rising edge of rd or cs . the total conversion time is therefore: t cwr = t wr (250ns) + t csh (0ns) to t rd (250ns) + t acc1 (160ns) = 660ns. pipelined operation besides the two standard wr-rd mode options, pipe - lined operation can be achieved by connecting wr and rd together (figure 6). with cs low, driving wr and rd low initiates a conversion and reads the result of the previ - ous conversion concurrently. analog considerations reference figures 7aC7c show some reference connections. v ref+ and v ref- inputs set the full-scale and zero-input voltages of the adc. the voltage at v ref- defines the input that produces an output code of all zeros, and the voltage at v ref+ defines the input that produces an output code of all ones. figure 3. rd mode timing (mode = 0) figure 5. wr-rd mode timing (t rd > t intl ), fastest operating mode (mode = 1) figure 4. wr-rd mode timing (t rd > t intl ) (mode = 1) figure 6. pipelined mode timing ( wr = rd ) (mode = 1) t p t inth t csh t dh t crd t acc0 with external pullup t css t rdy cs rd int d0?d 7v alid da ta rdy va lid da ta t acc2 t dh t inth t csh t wr t css cs wr int d0?d7 rd t rd t p t read2 t intl t cwr t csh t p t rd t css t ri t read1 t acc1 t dh t inth t wr da ta va lid cs wr rd int d0?d7 t ihwr t id t wr t p new da ta old da ta rd, wr int d0?d7 t intl downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 10 the internal resistances from v ref+ and v ref- may be as low as 1k. since current is still drawn by the reference inputs during power-down, reference supply current can be reduced during shutdown by using the circuit shown in figure 7d. a logic-level n-channel mosfet, connected between v ref- and ground, disconnects the reference load when the adc enters power-down. ( pwrdn = low). the fet should have no more than 0.5 of on-resistance to maintain accuracy. bypassing a 4.7f electrolytic in parallel with a 0.1f ceramic capacitor should be used to bypass v dd to gnd. these capacitors should have minimal lead length. the reference inputs should be bypassed with 0.1f capacitors, as shown in figures 7aC7c. input current figure 8 shows the equivalent circuit of the converter input. when the conversion starts and wr is low, v in is connected to 16 0.6pf capacitors. during this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches (about 2k). in addition, about 12pf of stray capaci - tance must be charged. the input can be modeled as an equivalent rc network (figure 9). as source impedance increases, the capacitors take longer to charge. the typical 22pf input capacitance allows source resis - tance as high as 2.2k without setup problems. for larger resistances, the acquisition time (t p ) must be increased figure 7a. power supply as referencefigure 7b. external reference, +2.5v full scale figure 7c. input not referenced to gnd figure 7d. an n-channel mosfet switches off the reference load during power-down gnd v in- 10 v in v in+ 1 v dd v ref+ v ref- 2012 4.7f 0.1f +5v 11 max153 0.1f +2.5v 20 4.7f 0.1f +5v gnd v in- 10 v in v in+ 1 v dd v ref+ v ref- 1211 max153 max584 +2.5v v in v in+ v in- 1 gndv dd v ref+ v ref- 1020 12 4.7f 0.1f 0.1f +5v 11 max153 0.1f * *current path must still exist from v in- to gnd max584 v dd v in+ pwrdn 20 v ref+ v ref- pwrdn 1211 0.1f0.1f 18 max153 0.1f n-fet downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 11 conversion rate the maximum sampling rate (f max ) for the max153 is achieved in the wr-rd mode (t rd < t intl ) and is calcu - lated as follows: max wr rd ri p max max 1 f t t tt 1 f 250ns 250ns 150ns 165ns f 1.23mhz = + ++ = +++ = where t wr = write pulse width t rd = delay between wr and rd pulses t ri = rd to int delay t p = delay time between conversions signal-to-noise ratio and effective number of bits signal-to-noise ratio (snr) is the ratio of the rms ampli - tude of the fundamental input frequency to the rms amplitude of all other analog-to-digital output values. the output band is limited to one-half the a/d sample (conver - sion) rate. this ratio usually includes distortion as well as noise components. for this reason, the ratio is sometimes referred to as signal-to-noise plus distortion. the theoretical minimum a/d noise is caused by quanti - zation error and results directly from the adcs resolution: snr = (6.02n + 1.76)db, where n is the number of bits of resolution. therefore, a perfect 8-bit adc can do no better than 50db. the fft plot ( typical operating characteristics ) shows the result of sampling a pure 200khz sinusoid at a 1mhz rate. this fft plot of the output shows the output level in various spectral bands. the effective resolution, or effective number of bits, the adc provides can be measured by transposing the equation that converts resolution to snr: n = (snr - 1.76)/6.02. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal (in the frequency band above dc and below one-half the sample rate) to the fundamental itself. this is expressed as: 2 22 2 2 34 n 1 (v + v +v + ... +v ) thd 20 log v ???? = ???? ?? where v 1 is the fundamental rms amplitude, and v 2 to v n are the amplitudes of the 2nd through nth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is the ratio of the funda - mental rms amplitude to the amplitude of the next largest spectral component (in the frequency band above dc and below one-half the sample rate). usually this peak occurs at some harmonic of the input frequency, but if the adc is exceptionally linear, it may occur only at a random peak in the adcs noise floor. intermodulation distortion an fft plot of intermodulation distortion (imd) is gener - ated by sampling an analog input applied to the adc. this input consists of very low distortion sine waves at two frequencies. a 2048 point plot for imd of the max153 is shown in the typical operating characteristics . figure 8. equivalent input circuit figure 9. rc network equivalent input model v in v in r on r in 1 c max153 v in v in 2k r 1 12pf max153 10pf downloaded from: http:///
max153 1msps, p-compatible, 8-bit adc with 1a power-down www.maximintegrated.com maxim integrated 12 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos +denotes a lead(pb)-free/rohs-compliant package. *contact factory for dice specifications. **contact factory for availability of ssop packages ordering information package type package code outline no. land pattern no. 20 pdip p20+3 21-0043 20 so(w) w20+2 21-0042 90-0108 20 ssop a20+1 21-0056 90-0094 part temp range pin-package max153cap+ 0c to +70c 20 ssop** max153cpp+ 0c to +70c 20 pdip max153cwp+ 0c to +70c 20 so(w) max153c/d 0c to +70c dice* max153eap+ -40c to +85c 20 ssop* * max153epp+ -40c to +85c 20 pdip max153ewp+ -40c to +85c 20 wide so downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max153 1msps, p-compatible, 8-bit adc with 1a power-down ? 2012 maxim integrated products, inc. 13 revision history revision number revision date description pages changed 0 7/92 initial release 1 10/93 corrected die topography 11 2 1/12 removed military packages 1C5 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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